Regviz

Renesas Electronics /R7FA6M3AH /GLCDC /BG_SYNC

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as BG_SYNC

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Renesas Electronics/R7FA6M3AH/GLCDC/BG_SYNC#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (others)HP0 (others)VP

HP=others, VP=others

Description

Background Plane Setting Synchronization Position Register

Fields

HP

Background plane horizontal synchronization signal assertion position on the basis of pixel clock (PXCLK).

0 (0x0): Setting prohibited

0 (others): (HP)th line (pixels)
VP

Background plane vertical synchronization signal assertion position on the basis of line.

0 (0x0): Setting prohibited

0 (others): (VP)th line

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data